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MICRO-38
November 12-16, 2005
New Hilton Diagonal Mar Hotel Barcelona, Spain | 
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Technical Program
Sunday, Nov. 13th | |
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| 20:00 | Welcome cocktail. Registration desk opens. |
Monday, Nov. 14th | |
| 8:30 | Opening |
| 9:00 | Keynote I Chair: Alex Veidenbaum |
| The Cell Processor Architecture
Peter Hofstee, IBM | |
| 10:00 | Session I: Register File and Memory System Chair: David Kaeli |
| How to Fake 1000 registers David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt The University of Michigan | |
| Reducing Instruction Fetch Cost by Packing Instructions into Register Windows Stephen Hines, Gary Tyson, David Whalley Florida State University | |
| Efficient Use of Invisible Registers in Thumb Code Arvind Krishnaswamy, Rajiv Gupta The University of Arizona | |
| 11:30 | Coffee Break |
| 12:00 | Session II: Processor Design and Optimization Chair: Daniel Jimenez |
| Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution Hyesoon Kim, Onur Mutlu, Yale N. Patt The University of Texas at Austin Jared Stark, Intel Corporation | |
| A Criticality Analysis of Clustering in Superscalar Processors Pierre Salverda, Craig Zilles UIUC | |
| Incremental Commit Groups for Non-Atomic Trace Processing Matt T. Yourst, Kanad Ghose State University of New York at Binghamton | |
| 13:30 | Lunch |
| 15:00 | Session III: Multithreading / CMP Chair: Alex Ramirez |
| Pinot: Speculative Multi-threading Processor Architecture Exploiting Parallelism over a Wide Range of Granularities Taku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita NEC | |
| Dynamic Helper Threaded Prefetching on the Sun UltraSPARC-CMP Processor Jiwei Lu, Abhinav Das, Wei-Chung Hsu, University of Minnesota Santosh G. Abraham, Khoa Nguyen, Sun Microsystems | |
| Automatic Thread Extraction with Decoupled Software Pipelining Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August Princeton University | |
| 16:30 | Coffee Break |
| 17:00 | Session IV: Compilers and Dynamic optimization Chair: Bilha Mendelson |
| Exploiting Vector Parallelism in Software Pipelined Loops Samuel Larsen, Rodric Rabbah, Saman Amarasinghe MIT CSAIL | |
| Continuous Path and Edge Profiling Michael D. Bond, Kathryn S. McKinley UT Austin | |
| Improving Region Selection in Dynamic Optimization Systems David J. Hiniker, Microsoft Michael D. Smith, Harvard University Kim Hazelwood, University of Virginia | |
| 20:30 | Welcome Reception |
Tuesday, Nov 15th. | |
| 9:00 | Keynote II Chair: Mateo Valero |
| The Future Evolution of High-Performance Microprocessors Norm Jouppi, HP Labs | |
| 10:00 | Session V: Memory Disambiguation and Optimization Chair: Konrad Lai |
| Scalable Store-Load Forwarding via Store Queue Index Prediction Tingting Sha, Milo M. Martin, Amir Roth University of Pennsylvania | |
| Address-Indexed Memory Disambiguation and Store-to-Load Forwarding Samuel S. Stone, Kevin M. Woley, Matthew I. Frank University of Illinois at Urbana-Champaign | |
| Store Memory-Level Parallelism Optimizations for Commercial Applications Yuan Chou, Lawrence Spracklen, Santosh Abraham Sun Microsystems | |
| 11:30 | Coffee Break |
| 12:00 | Session VI: Processor Design Chair: Nick Carter |
| A Mechanism for Online Diagnosis of Hard Faults in Microprocessors Fred A. Bower, Duke University and IBM Daniel J. Sorin, Sule Ozev, Duke University | |
| μComplexity: Estimating Processor Design Effort Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau Computer Engineering, UC Santa Cruz | |
| Cost Sensitive Modulo Scheduling in a Loop Accelerator Systhesis System Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott Mahlke University of Michigan | |
| 13:30 | Lunch |
| 14:30 | Session VII: Speculation Chair: Toshinori Sato |
| Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns Onur Mutlu, Hyesoon Kim, Yale N. Patt University of Texas at Austin | |
| Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors Meyrem Kırman, Nevin Kırman, and José F. Martínez Cornell University | |
| ReSlice: Selective Re-Execution of Long-Retired Mis-peculated Instructions Using Forward Slicing Smruti Ranjan Sarangi, Wei Liu, Josep Torrellas, Yuanyuan Zhou University of Illinois at Urbana Champaign | |
| 16:30 | Excursion to the Dali museum at Figueres, followed by banquet at Peralada Castle (from 21:00 to midnight) |
Wednesday, Nov 16th. | |
| 9:00 | Session VIII: Power, Temperature and Fault Management Chair: Andreas Moshovos |
| A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance Qiang Wu, Margaret Martonosi, Douglas W. Clark, Princeton University Vijay Reddi, Dan Connors, University of Colorado Youfeng Wu, Jin Lee, Intel Corporation David Brooks, Harvard University | |
| Thermal Management of On-Chip Caches Through Power Density Minimization Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea Ismail Northwestern University | |
| Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar Purdue ECE | |
| A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation Tzvetan S. Metodi, Darshan D. Thaker, Frederic T. Chong, University of California at Davis Andrew W. Cross, Isaac L. Chuang, Massachusetts Institute of Technology | |
| 11:00 | Coffee Break |
| 11:30 | Session IX: Processor Architecture and Programming Chair: Koen De Bosschere |
| "Flea-flicker" Multipass pipelining: An Alternative to the High-Power Out-of-Order Offense Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu University of Illinois | |
| The TM3270 Media-Processor Stamatis Vassiliadis, TU Delft Jan-Willem van de Waerdt, TU Delft / Philips Seminconductors Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans van Antwerpen, Philips Semiconductors | |
| Stream Programming on General-Purpose Processors Jayanth Gummaraju, Mendel Rosenblum Stanford University | |
| Shader Performance Analysis on a Modern GPU Architecture Victor Moya del Barrio, Carlos Gonzalez Rodriguez, Jordi Roca Monfort, Agustin Fernandez Jimenez, Department of Computer Architecture, UPC Roger Espasa Sans, Department of Computer Architecture, UPC and Intel | |