Following performance and power, reliability has emerged as the latest challenge in microarchitecture. Various developments have combined to make reliability a concern: soft-error rate is projected to increase with scaling; variability due to non-deterministic placement of dopant atoms and channel length is increasing design margins; better than worst-case design techniques for power/performance require error detection/correction; aggressive application of power-saving mechanisms such as clock- and Vdd-gating are increasing voltage droops; the verification manpower budget is becoming a significant part of the design effort; oxide breakdown and electromigration are decreasing processor lifetimes…

WAR serves as a forum for microarchitectural solutions to address such current and emerging reliability-related issues. Although the focus is on architecture, work on synergistic circuit, compiler, OS and network solutions is also encouraged. Through sharing ideas and fermenting further research, the inaugural workshop will hopefully serve to make WAR an annual event in this exciting new area.

Important Dates

Paper Submission : September 22, 2005

Author Notification: October 16, 2005

Camera Ready Due: October 23, 2005

last updated on : 01.07.2006